(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to increase the collector-emitter breakdown voltage of a Buried layer Pinched Collector Bipolar, (BPCB), device.
(2) Description of Prior Art
The addition of bipolar devices, to designs comprised with complimentary metal oxide semiconductor, (CMOS), devices, have allowed the performance of these BiCMOS, semiconductor chips, in terms of switching speeds, or frequency response, (Ft), to be increased when compared to counterpart designs, comprised with only CMOS devices. In addition the complexity of fabricating a BiCMOS chip, is reduced by also using, or sharing, several CMOS fabrication sequences, for the construction of the bipolar devices. For example an NPN bipolar device, featuring a N type, buried subcollector region, fabricated simultaneously with CMOS devices, can result in an Ft of about 5 to 20 Ghz, with a collector-emitter breakdown voltage, (BVCEO), of about 8 to 10 volts. The use of a P type, buried layer, in place of the N type, buried subcollector, results in an increase in BVCEO to about 20 volts, however at the expense of Ft which now is less than 5 Ghz, due to a lower than desired N well concentration, used to obtain the BVCEO increases.
This invention will describe a bipolar device fabrication procedure, blended together with the fabrication of CMOS devices, in which the bipolar device, of the BiCMOS chip, is fabricated featuring a P type field ring, located underlying a field oxide region, and between the base and collector regions of the bipolar device. The use of the P type field ring increases the BVCEO parameter, while allowing the use of heavier N well concentrations, thus resulting in increases in Ft to be realized. The BVceo increase resulted from a reduction in the local dopant concentration of the N well region, as a result of the P type field ring region, allowing BVCEO values of about 90 volts to be realized. Prior art, such as Chi, in U.S. Pat. No. 5,866,003, as well as Miscaller et al, in U.S. Pat. No. 4,966,858, describe buried layers for a bipolar device, and polysilicon field plates for a lateral bipolar device, however these prior arts do not suggest the use of field ring region, located between the base and collector regions, of a bipolar device, fabricated using the same process steps used to fabricate a CMOS device.